1. Field of the Invention
The present invention relates to the structure of a dielectric layer between two adjacent wiring lines. More particularly, the invention relates to the structure of a dielectric layer that can reduce the parasitic capacitance between two coplanar copper wiring lines.
2. Description of the Prior Art
Resistance-capacitance (RC) time delay is a phenomenon that is caused by adjacent metallic wiring lines in which each line is carrying an electric current, and it is a serious problem in multi-level metalization processes for manufacturing integrated circuits (IC). RC time delays usually lead to reduced response and poor electrical performance of an IC. The response and performance become worse as the spacing between two adjacent metallic wiring lines decreases.
RC time delay is a product of the resistance R of the metallic wiring lines and the parasitic capacitance C formed between them. Minimal RC time delays are desirable. In essence, there are two approaches to reduce RC time delay: a) using conductive materials with a lower resistance as a wiring line or, b) reducing the parasitic capacitance.
Obviously, copper is a good choice owing to its low resistance (1.67 .mu..OMEGA.-cm) instead of Al--Cu(5%) alloy which is mostly commonly used in current multilevel metalization processes. However, with the ever-increasing demand on performance, changing the metallic material appears to be inadequate to support future requirements. Consequently, some organic dielectric materials with low dielectric constants, such as polyimide (PI) and HSQ (hydrogen silsequioxane) etc., are rapidly coming into use to reduce parasitic capacitance. Unfortunately, most organic dielectric materials have metal adhesion issues and stability problems in a thermal environment.